1. Field of the Invention
The present invention relates to a high breakdown voltage output circuit for shifting a level of a low-voltage output signal to output a high-voltage output signal.
2. Description of the Related Art
In general, since an IC for driving a light-emitting display such as an electroluminescence (EL) display or a plasma display panel (PDP) requires a high drive voltage, drive ICs having high breakdown voltage characteristics have been used. In an output circuit in the drive IC, high breakdown voltage characteristics, a short switching time, and low power consumption have been demanded. For this reason, a CMOS circuit is used to receive an input signal and output a low-voltage signal, and a high-voltage signal obtained by shifting the level of the low-voltage signal is output from a push-pull output stage.
FIG. 1 is a circuit diagram showing a conventional output circuit used for the above-mentioned drive IC. A CMOS inverter 33 is inserted between a low-voltage power source V.sub.DD and a ground voltage V.sub.SS. The CMOS inverter 33 includes a p-channel MOS transistor 31 and an n-channel MOS transistor 32, and receives an input signal In. The emitter of a high breakdown voltage pnp transistor 34 is connected to a high-voltage power source V.sub.CC. The transistor 34 has a multicollector structure. One collector of the transistor 34 is connected to its base. The base of the pnp transistor 34 is connected to the drain of an n-channel DMOS (double diffused MOS) transistor 35, the gate of which is connected to an output node of the CMOS inverter 33, and the source of which is connected to the ground voltage V.sub.SS. The other collector of the pnp transistor 34 is connected to the drain of an output pull-down n-channel DMOS transistor 36. The gate of the transistor 36 receives the input signal In, and the source of the transistor 36 is connected to the ground voltage V.sub.SS. In addition, the other collector of the transistor 34 is connected to the gate of an output pull-up n-channel DMOS transistor 37. The drain of the transistor 37 is connected to the high-voltage power source V.sub.CC. An anode-cathode path of a Zener diode 38 is connected to a gate-source path of the transistor 37. An output signal Out is output from the source of the n-channel DMOS transistor 37.
In the circuit with the above arrangement, when the input signal In is set at "L" level, the transistor 31 in the CMOS inverter 33 is turned on, and the transistor 32 is turned off. Therefore, a signal set at V.sub.DD level is output from the output terminal of the CMOS inverter 33, and the transistor 35 is turned on. Therefore, the level shift transistor 34 is turned on, and a voltage drop occurs across the Zener diode 38 in response to this ON current, thus turning on the transistor 37. As a result, the output signal Out goes to "H", i.e., V.sub.CC level.
When the input signal In is set at "H" level, the transistor 31 in the CMOS inverter 33 is turned off, the transistor 32 is turned on, the transistor 35 is turned off, and the transistor 34 is turned off. Therefore, the transistor 37 is turned off. On the other hand, the input signal In is set at "H" level, so that the transistor 36 is turned on, and the output signal Out goes to "L" level.
In the circuit shown in FIG. 1, a voltage V.sub.GS of the gate-source path of the output pull-up transistor 37 is determined in accordance with a Zener voltage V.sub.Z of the Zener diode 38. When the Zener voltage V.sub.Z is set so that the voltage V.sub.GS exceeds a threshold voltage Vth of the transistor 37, the transistor 37 is turned on. A drain current ID of the MOS transistor 37 is defined as follows: ##EQU1## where .mu. is mobility of electrons, .epsilon..sub.OX is a dielectric constant of a gate oxide film in the transistor 37, t.sub.OX is a thickness of the gate oxide film, W is a channel width, L is a channel length, and .epsilon..sub.O (=8.854.times.10.sup.-14 F/cm) is a vacuum dielectric constant.
Thus, the drain current I.sub.D exhibits square characteristics. Therefore, when the threshold voltages Vth of the transistor 37 are varied, the value of the drain current I.sub.D is largely changed. Similarly, a variation in threshold voltage of the output pull-down transistor 36 causes a change in drain current. Thus, in the manufacturing process, a desired threshold voltage of the transistor to be formed on a semiconductor chip is deviated from a threshold voltage of the transistor which was manufactured in practice. As a result, the drain current of the output transistor is changed, and saturation voltages of the output transistor are varied. Therefore, in this output circuit which operates in a saturation region of the output transistor, a delay of output rise time is different from that of output fall time.
Thus, in the conventional output circuit, when the threshold voltages of the output transistor are varied, a drain current of the output transistor is changed. Therefore, stable rising and falling characteristics cannot be obtained.